Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography, among others, is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
A lithographic process, as described above, is performed to selectively remove portions of a resist material overlaying the surface of a wafer, thereby exposing underlying areas of the specimen on which the resist is formed for selective processing such as etching, material deposition, implantation, and the like. Therefore, in many instances, the performance of the lithography process largely determines the characteristics (e.g., dimensions) of the structures formed on the specimen. Consequently, the trend in lithography is to design systems and components (e.g., resist materials) that are capable of forming patterns having ever smaller dimensions. In particular, the resolution capability of the lithography tools is one primary driver of lithography research and development.
Lithographic processes utilizing electromagnetic energy in the form of extreme ultraviolet (EUV) light are being developed for selective exposure of the resist. EUV radiation generated by an EUV radiation source is directed to a reticle surface, reflected from the reticle surface, and projected onto a wafer in a clean vacuum environment. The reticle surface is patterned and the reflected light projects this pattern onto the wafer. To achieve ever smaller patterned feature sizes, the feature sizes of reticle patterns continue to shrink. Consequently, particle contamination requirements on the reticle surface continue to become more stringent.
In traditional optical projection lithography, a pellicle is used to protect the reticle. This pellicle remains in place during all stages of the lithography process. When a pellicle is used, particles settle on the pellicle rather than the reticle. Cleaning the pellicle poses fewer dangers to the integrity of the reticle since the reticle is protected by the pellicle during any cleaning operations. The pellicle also minimizes the impact of particle contamination by separating any particles that have settled on its surface from the reticle pattern by a distance corresponding to the pellicle standoff-distance. This distance keeps the particles away from the image plane of the imaging system (the reticle patterned surface), thus minimizing their impact on the image projected onto the wafer.
Unfortunately, a pellicle is not currently used in EUV applications because the short wavelengths of light are easily absorbed when transmitted through gases or solids. Currently there are no robust materials sufficiently transparent to EUV that can be used to make a pellicle. Without available materials to cover the patterned surface of an EUV reticle to protect it from particle contamination, the patterned surface of EUV reticles is exposed to the process environment during lithographic operations and in some inspection operations. Although work is being done to identify a more robust, transmissive pellicle, even if such a pellicle were to become available, particle contamination requirements will remain stringent as feature sizes continue to shrink. As a result, maintaining particle control and cleanliness of EUV reticles both inside and outside semiconductor processing equipment is a significant issue.
In an effort to reduce particle contamination, a standard EUV pod (compliant with SEMI standard E152-0709) has been developed. An EUV pod includes an outer carrier, commonly referred to as a Reticle SMIF Pod (RSP), and an inner pod, commonly referred to as an EUV Inner Pod (EIP). The RSP is suitable for transporting EUV masks among different production stations and sites. The EIP is a protective enclosure that allows the reticle to remain within a protective environment until inside vacuum and near the reticle stage. During pumpdown to vacuum or vent to atmospheric pressure, particles can be stirred up and deposited onto a reticle surface. The EIP allows the reticle to remain within a protective environment until inside vacuum and near the stage. A number of publications describe the development of an EUV Inner Pod (EIP) to protect the reticle. Exemplary publications include: “EXTATIC, ASML's—tool development for EUVL,” Hans Meiling, et al., Emerging Lithographic Technologies VI, Proceedings of SPIE, Vol. 4688 (2002), “Evaluation Results of a New EUV Reticle Pod Having Reticle Grounding Paths,” Kazuya Ota, et al., Extreme Ultraviolet (EUV) Lithography II, Proceedings of SPIE, Vol. 7969 (2011), and “ASML Approach to EUV Reticle Protection,” Brian Blum, et al., presentation at Dallas EUV Symposium, Nov. 13, 2002, the entire subject matter of each is incorporated herein by reference.
Traditionally, the EIP is opened in vacuum to allow the reticle to be loaded onto an electrostatic chuck. The use of an electrostatic chuck is expensive and creates many particles that accumulate on the backside of the reticle. Alternatively, the reticle may be loaded directly onto the reticle stage using a clamp mechanism. This has a number of disadvantages. First, the clamping process generates a significant number of particles. In the clean vacuum environment required for EUV lithographic or inspection processing, control of these particles is difficult. Moreover, the generation of these particles in the processing environment is undesirable. Second, the EIP was developed specifically for use with a reticle stage with an electrostatic chuck. The limitations of the EIP design make it difficult to use in applications with a different method of holding the reticle, namely clamping. This complicates the stage design and also makes it difficult to control particles created during the clamping process.
The importance of inspection of EUV reticles continues to grow as the dimensions of semiconductor devices continue to shrink. Improved methods and systems for handling EUV reticles in a reticle inspection system that minimize the number of particles added to the reticle are desired.